1. Field of the Invention
The present invention relates generally to self-timed clocking transfer control circuits, and more specifically, to a self-timed clocking transfer control circuit for controlling transfer of a transfer request signal.
2. Description of the Related Art
Data transmission apparatuses employing an asynchronous hand shaking method are sometimes used for data processing apparatuses for input/output of data using an FIFO (First In First Out) memory or for data driven type information processing. In such a data transmission apparatus, a plurality of data transmission circuits are connected in series to constitute a data transmission path, and these data transmission circuits transmit/receive a transfer request signal for data and a transfer acknowledge signal to perform autonomous data transfer. The transfer request signal is a signal requesting a next stage data transmission circuit to receive data. The transfer acknowledge signal is a signal indicating to another data transfer circuit in the preceding stage whether or not to permit data transfer.
FIG. 1 is a block diagram showing one example of a conventional data transmission apparatus employing a hand shaking method. Referring to FIG. 1, the data transmission apparatus includes data transmission circuits 10, 20 and 30, and logic circuits 16, 26, and 36. Circuits 10, 16, 20, 26, 30, and 36 are connected in series in this order. In the data transmission apparatus shown in FIG. 1, data is transferred through data transmission paths 10, 20, and 30, and the data is sequentially processed by logic circuits 16, 26, and 36.
Data transmission circuits 10, 20, and 30 include data holding circuits 12, 22, and 32, and transfer control circuits 14, 24, and 34, respectively.
FIG. 2 is a block diagram showing data transmission circuit 10 shown in FIG. 1. In FIG. 2, although only the part concerning data transmission circuit 10 is illustrated in the form a block diagram, the other transmission circuits 20 and 30 have the same structure as data transmission circuit 10. Therefore, a detailed description of data transmission circuits 20 and 30 is not repeated here.
Referring to FIG. 2, data transmission circuit 10 includes self-timed clocking transfer control circuit 14 and data holding circuit 12 formed of D type flipflops. The self-timed clocking transfer control circuit is defined as in the following. There exists a data transmission control method by which a transfer request signal and a transmission acknowledge signal are transmitted/received between adjacently connected data transmission circuits in a data transmission path, and data transfer is performed asynchronously according to these signals and with at least preset time delays. Such control is called self-synchronous type transfer control. And the circuit for controlling such data transfer is called self-timed clocking transfer control circuit.
Transfer control circuit 14 includes a transfer request signal input terminal (CI input terminal) 40 for receiving a transfer request signal CI (C10) from a preceding stage (not shown), a transfer acknowledge output terminal (RO output terminal) 42 for outputting a transfer acknowledge signal RO (R10) indicating to the preceding stage acknowledgement or prohibition of transfer, a transfer request signal output terminal (CO output terminal) 44 for outputting a transfer request signal CO (C10) to a succeeding stage (not shown), a transfer acknowledge input terminal (RI input terminal) 46 for receiving from the succeeding stage a transfer acknowledge signal RI (R20) indicating acknowledgement or prohibition of transfer, and an output terminal for providing data holding circuit 12 (shown in FIG. 2) with a clock pulse CP for controlling data holding operation.
Upon receiving transfer request signal CI from the preceding stage, transfer control circuit 14 outputs transfer request signal CO to the succeeding stage and clock pulse CP to data holding circuit 12, if transfer acknowledge signal RI from the succeeding stage indicates acknowledgement. Data holding circuit 12 responds to clock pulse CP to hold data DI provided from the preceding stage and provides the held data to the succeeding stage as output data DO.
Referring back to FIG. 1, the CO output terminal of transfer control circuit 14 is connected to the CI input terminal of transfer control circuit 24. A transfer request signal C20 is applied from transfer control circuit 14 to transfer control circuit 24. The CI input terminal of transfer control circuit 34 is connected to the CO output terminal of transfer control circuit 24. A transfer request signal C30 is applied from transfer control circuit 24 to transfer control circuit 34.
The RO output terminal of transfer control circuit 24 is connected to the RI input terminal of transfer control circuit 14. Transfer acknowledge signal R20 is applied from transfer control circuit 24 to transfer control circuit 14. The RO output terminal of transfer control circuit 34 is connected to the RI input terminal of transfer control circuit 24. A transfer acknowledge signal R30 is applied from transfer control circuit 34 to transfer control circuit 24.
The CI input terminal of transfer control circuit 14 is connected to the CO output terminal of the preceding stage which is not shown. Transfer request signal C10 is applied from the transfer control circuit in the preceding stage which is not shown to transfer control circuit 14. The RO output terminal of transfer control circuit 14 is connected to the RI input terminal of the transfer control circuit in the preceding stage which is not shown. Transfer acknowledge signal R10 is applied from transfer control circuit 14 to the transfer control circuit of the preceding stage.
The CO output terminal of transfer control circuit 34 is connected to the CI input terminal of a transfer control circuit in the succeeding stage which is not shown. A transfer request signal C40 is applied from transfer control circuit 34 to the transfer control circuit in the succeeding stage. The RI input terminal of transfer control circuit 34 is connected to the RO output terminal of the transfer control circuit in the succeeding stage which is not shown. A transfer acknowledge signal R40 is applied from the transfer control circuit of the succeeding stage to transfer control circuit 34.
In FIG. 1, even if data transmission circuit 10 holds data, the data is not transferred from data transmission circuit 10 to data transmission circuit 20, if, for example, data transmission circuit 20 in the succeeding stage holds data as well. If data transmission circuit 20 in the succeeding stage does not hold data (or transits to such a state) data held in data transmission circuit 10 is sent to data transmission circuit 20 over at least preset time delay.
FIG. 3 is a circuit diagram showing one example of a conventional self-synchronous transfer control circuit 14.
Referring to FIG. 3, transfer control circuit 14 further includes a master reset signal (MR) input terminal 48.
Transfer control circuit 14 further includes an RS-flipflop 50, a 4-input NAND gate 52, an RS-flipflop 54, inverters 56 and 58, a delay element 60, and an inverter 62.
RS-flipflop 50 includes cross-connected two NAND gates 70 and 72. NAND gate 72 has three inputs, one of which is a reset input. Another input of NAND gate 72 is connected to the input terminal 48 of master reset signal MR. One input of NAND gate 70 is a set input 74. The outputs of NAND gates 70 and 72 are connected to each other's remaining inputs. The output of NAND gate 70 is also the Q output 78 of RS-flipflop 50.
A first input of 4-input NAND gate 52 is connected to CI input terminal 40. A second input is connected to the Q output 78 of RS-flipflop 50. A third input is connected to RI input terminal 46. A fourth input is connected to the output of inverter 58. The output G of NAND gale 52 is connected to the reset input of RS-flipflop 54.
RS-flipflop 54 includes cross-connected two NAND gates 80 and 82. NAND gate 82 has three inputs, one of which is a reset input. Another input of NAND gate 82 is connected to the input terminal 48 of master reset signal MR. One input of NAND gate 80 is a set input 81. The outputs of NAND gates 80 and 82 are connected to each other's remaining inputs. The output of NAND gate 80 is also the Q output 83 of RS-flipflop 54.
The output of inverter 56 becomes clock pulse CP to data holding circuit 12 shown in FIG. 2. The output of inverter 56 is also connected to the input of inverter 58. The output of inverter 58 is connected to the fourth input of NAND gate 52 and the input of delay element 60.
The output of delay element 60 is connected to CO output terminal 44.
The input of inverter 62 is connected to the Q output 78 of flipflop 50. The output of inverter 62 is connected to RO output terminal 42.
In FIG. 3, the pulse-shaped transfer request signal CI from the preceding stage is applied to CI input terminal. Transfer acknowledge signal RO is output from RO output terminal 42 to the preceding stage. The pulse-shaped transfer request signal CO is output from CO output terminal 44 to the succeeding stage. Transfer acknowledge signal RI is applied to RI input terminal 46 from the succeeding stage. Master reset signal MR is applied to MR input terminal 48.
The operation of RS-flipflop 50 will be briefly described. RS-flipflop 50 is set upon receiving an "L" level pulse S at its set input 74. An "H" level signal appears at the Q output 78 of RS-flipflop 50. RS-flipflop 50 is reset upon receiving an "L" level reset pulse R at its reset input 76. RS-flipflop 50 outputs the "L" level at its Q output 78. When master reset signal MR attains the "L" level, flipflop 50 is reset and the "L" level appears at its Q output 78. Accordingly, an "H" level transfer acknowledge signal RO is output from RO output terminal 42.
The operation of RS-flipflop 54 is the same as that of RS-flipflop 50, and therefore a detailed description thereof is not repeated here. It should be noted that the output of RS-flipflop is a Q output.
Note that transmission acknowledge signal RO in its "H" level indicates acknowledgement of transfer, while in its "L" level prohibition of transfer. Transfer request signal CI in its "L" level indicates that data transfer is being requested from the preceding stage, while in its "H" level indicates that data transfer is not requested from the preceding stage.
Referring to FIGS. 3 and 4, transfer control circuit 14 shown in FIG. 3 operates as follows.
An "L" level master reset pulse MR is applied to MR input terminal 48. In response to this master reset pulse MR transfer control circuit 14 is initialized. More specifically, RS-flipflops 50 is reset and RS-flipflop 54 is set. They output an "L" level and an "H" level, respectively. Accordingly, an "H" level transfer acknowledge signal RO is output from RO output terminal 42 (FIG. 4(b)). After a prescribed time delay, an "H" level transfer request signal CO is output from CO output terminal 44 (FIG. 4(e)). The output of inverter 56 is in an "L" level. Clock pulse CP is therefore in an "L" level (FIG. 4(d)).
Based on transfer acknowledge signal RO permitting transfer, a transfer control circuit in the preceding stage (not shown) pulls transfer request signal CI to CI input terminal 40 to an "L" level (FIG. 4(a)). In response, RS-flipflop 50 is set, and the potential of its Q output 78 attains the "H" level. In response, output signal RO from RO output terminal 42 attains the "L" level (the state prohibiting transfer) (FIG. 4(b)). Thus, the preceding stage is prohibited from further transferring data to data transfer circuit 10 including this transfer control circuit 14 (see FIG. 2).
After a prescribed time period, transfer request signal CI at CI input terminal 40 attains the "H" level (FIG. 4(a)). NAND gate 52 outputs "L" to its output node G, when the Q output of RS-flipflop 50 is in the "H" level, transfer request signal CI returns to the "H" level, transfer request signal CO is in the "H" level, and transfer acknowledge signal RI is the "H" level. More specifically, NAND gate 52 outputs the "L" level to its output node G if RS-flipflop 50 stores reception of the data transfer request signal from the preceding stage, if transfer request signal CI returns to the "H" level, if transfer control circuit 14 is not outputting data transfer request signal CO to the succeeding stage which is not shown, and if the succeeding stage outputs transfer acknowledge signal RI indicating permission of transmission (FIG. 4(c)).
When the output node G of NAND gate 52 attains the "L" level, RS-flipflop 50 is reset. RS-flipflop 54 is reset as well. The output of RS-flipflop 54 attains the "L" level. The output of inverter 56 rises to the "H" level. More specifically, clock pulse CP to a corresponding data holding circuit (of the data holding circuits) rises to the "H" level (FIG. 4(d)). Data holding circuit 12 (see FIG. 2) latches input data D in response to clock pulse CP, and sends the latched data as output data DO to logic circuit 16 in the succeeding stage (see FIG. 1).
The output of inverter 56 is further inverted by inverter 58, delayed by delay element 60 by a prescribed time period and output from CO output terminal 44. More specifically, transfer request signal CO attains the "L" level (FIG. 4(e)). Thus, data transfer is request to a transfer control circuit in the succeeding stage. A transfer control circuit of the next stage receives the transfer request signal from transfer control circuit 14.
The transfer control circuit in the succeeding stage (not shown) which has received transfer request signal CO brings its transfer acknowledge signal RI to the "L" level (FIG. 4(f)). More specifically, transfer acknowledge signal RI applied from the succeeding stage to transfer control circuit 14 is prohibited. When transfer acknowledge signal RI attains the "L" level, the signal RI is applied to the set input 84 of RS-flipflop 54 as set signal S. RS-flipflop 54 is set. In response, the output of inverter 54 attains the "L" level, and clock pulse CP attains the "L" level as well (FIG. 4(d)). Transfer request signal CO output from CO output terminal 44 returns to the "H" level (FIG. 4(e)). Thereafter, the data transfer circuit in the succeeding stage further transfers data to a data transfer circuit in the succeeding stage. Then, transfer acknowledge signal RI applied from the data transfer circuit in the succeeding stage to transfer control circuit 14 shown in FIG. 3 returns to the "H" level (FIG. 4(f)). Thus, data transmission circuit 10 (see FIG. 2) is permitted to transfer further data to a data transmission circuit in the next stage.
As described above, in the conventional transfer control circuit, if a data transmission circuit in a succeeding stage is empty, data is autonomously and sequentially transmitted to a data transmission path in the succeeding stage. More specifically, if transfer acknowledge signal RI is in the "H" level, transfer control circuit 14 autonomously transmits data to the data transmission circuit in the succeeding stage. Meanwhile, it is often necessary to control processing so as to gradually proceed data on a stage by stage basis for each data transmission circuit or logic circuit, when transfer timing of each data transmission circuit is to be verified or the content of processing by a logic circuit disposed between data transfer circuits is to be debugged. The conventional transfer control circuit cannot provide such and therefore it is difficult to confirm the operation of data transfer circuits in each stage.